URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Rev 128

Rev	Log message	Author	Age	Path
128	Reset all registers, constants now upper case.	rhoads	7346d 20h	/plasma/trunk/vhdl/mem_ctrl.vhd
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7546d 10h	/plasma/trunk/vhdl/mem_ctrl.vhd
95	register mem_write and mem_byte_sel for speed calculations	rhoads	8069d 13h	/plasma/trunk/vhdl/mem_ctrl.vhd
89	Use address_reg instead of address_data to break timing slow down	rhoads	8071d 07h	/plasma/trunk/vhdl/mem_ctrl.vhd
72	accurate_timing, cleanup, pipeline	rhoads	8079d 09h	/plasma/trunk/vhdl/mem_ctrl.vhd
56	Altera, added byte_sel_reg for tigher timing and avoid possible glitches	rhoads	8087d 14h	/plasma/trunk/vhdl/mem_ctrl.vhd
49	Fix pause while writting	rhoads	8098d 09h	/plasma/trunk/vhdl/mem_ctrl.vhd
47	Altera	rhoads	8105d 10h	/plasma/trunk/vhdl/mem_ctrl.vhd
43	Renamed M-lite to Plasma	rhoads	8185d 10h	/plasma/trunk/vhdl/mem_ctrl.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8217d 15h	/plasma/trunk/vhdl/mem_ctrl.vhd
8	Preparing to use dual-port memory for registers.	rhoads	8254d 09h	/plasma/trunk/vhdl/mem_ctrl.vhd
7	Made writes 4 cycles, improved mem_ctrl.vhd	rhoads	8259d 16h	/plasma/trunk/vhdl/mem_ctrl.vhd
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8263d 14h	/plasma/trunk/vhdl/mem_ctrl.vhd
2	MIPS-lite CPU core	rhoads	8482d 15h	/plasma/trunk/vhdl/mem_ctrl.vhd