URL https://opencores.org/ocsvn/plasma/plasma/trunk

Subversion Repositories plasma

[/] [plasma/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Rev 129

Rev	Log message	Author	Age	Path
129	Added reset_in to sensitivity list	rhoads	7213d 10h	/plasma/trunk/vhdl/mem_ctrl.vhd
128	Reset all registers, constants now upper case.	rhoads	7331d 21h	/plasma/trunk/vhdl/mem_ctrl.vhd
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7531d 11h	/plasma/trunk/vhdl/mem_ctrl.vhd
95	register mem_write and mem_byte_sel for speed calculations	rhoads	8054d 14h	/plasma/trunk/vhdl/mem_ctrl.vhd
89	Use address_reg instead of address_data to break timing slow down	rhoads	8056d 08h	/plasma/trunk/vhdl/mem_ctrl.vhd
72	accurate_timing, cleanup, pipeline	rhoads	8064d 10h	/plasma/trunk/vhdl/mem_ctrl.vhd
56	Altera, added byte_sel_reg for tigher timing and avoid possible glitches	rhoads	8072d 15h	/plasma/trunk/vhdl/mem_ctrl.vhd
49	Fix pause while writting	rhoads	8083d 10h	/plasma/trunk/vhdl/mem_ctrl.vhd
47	Altera	rhoads	8090d 11h	/plasma/trunk/vhdl/mem_ctrl.vhd
43	Renamed M-lite to Plasma	rhoads	8170d 11h	/plasma/trunk/vhdl/mem_ctrl.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8202d 16h	/plasma/trunk/vhdl/mem_ctrl.vhd
8	Preparing to use dual-port memory for registers.	rhoads	8239d 10h	/plasma/trunk/vhdl/mem_ctrl.vhd
7	Made writes 4 cycles, improved mem_ctrl.vhd	rhoads	8244d 17h	/plasma/trunk/vhdl/mem_ctrl.vhd
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8248d 15h	/plasma/trunk/vhdl/mem_ctrl.vhd
2	MIPS-lite CPU core	rhoads	8467d 16h	/plasma/trunk/vhdl/mem_ctrl.vhd