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[/] [plasma/] [trunk/] [vhdl/] [mlite_cpu.vhd] - Rev 264

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Rev Log message Author Age Path
264 Latch address and byte_we in mem_ctrl.vhd rhoads 6098d 21h /plasma/trunk/vhdl/mlite_cpu.vhd
203 Fixed stages comment rhoads 6337d 22h /plasma/trunk/vhdl/mlite_cpu.vhd
202 Defined outputing PC as stage #0 rhoads 6337d 23h /plasma/trunk/vhdl/mlite_cpu.vhd
194 Implemented BREAK and SYSCALL opcodes rhoads 6402d 18h /plasma/trunk/vhdl/mlite_cpu.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6748d 11h /plasma/trunk/vhdl/mlite_cpu.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7228d 10h /plasma/trunk/vhdl/mlite_cpu.vhd
128 Reset all registers, constants now upper case. rhoads 7365d 21h /plasma/trunk/vhdl/mlite_cpu.vhd
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7384d 11h /plasma/trunk/vhdl/mlite_cpu.vhd
120 Make generics "GENERIC" rhoads 7527d 00h /plasma/trunk/vhdl/mlite_cpu.vhd
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7565d 11h /plasma/trunk/vhdl/mlite_cpu.vhd
96 Simplify take_branch rhoads 8088d 15h /plasma/trunk/vhdl/mlite_cpu.vhd
83 Updated comments, accurate_timing on by default rhoads 8090d 08h /plasma/trunk/vhdl/mlite_cpu.vhd
73 pipeline, better reset rhoads 8098d 10h /plasma/trunk/vhdl/mlite_cpu.vhd
60 reset control rhoads 8106d 15h /plasma/trunk/vhdl/mlite_cpu.vhd
47 Altera rhoads 8124d 11h /plasma/trunk/vhdl/mlite_cpu.vhd
43 Renamed M-lite to Plasma rhoads 8204d 11h /plasma/trunk/vhdl/mlite_cpu.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8236d 16h /plasma/trunk/vhdl/mlite_cpu.vhd

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