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[/] [plasma/] [trunk/] [vhdl/] [mlite_cpu.vhd] - Rev 280

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Rev	Log message	Author	Age	Path
280	Fix comment	rhoads	6053d 08h	/plasma/trunk/vhdl/mlite_cpu.vhd
264	Latch address and byte_we in mem_ctrl.vhd	rhoads	6079d 18h	/plasma/trunk/vhdl/mlite_cpu.vhd
203	Fixed stages comment	rhoads	6318d 19h	/plasma/trunk/vhdl/mlite_cpu.vhd
202	Defined outputing PC as stage #0	rhoads	6318d 19h	/plasma/trunk/vhdl/mlite_cpu.vhd
194	Implemented BREAK and SYSCALL opcodes	rhoads	6383d 15h	/plasma/trunk/vhdl/mlite_cpu.vhd
139	Major changes -- updated to Plasma Version 3	rhoads	6729d 08h	/plasma/trunk/vhdl/mlite_cpu.vhd
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7209d 07h	/plasma/trunk/vhdl/mlite_cpu.vhd
128	Reset all registers, constants now upper case.	rhoads	7346d 18h	/plasma/trunk/vhdl/mlite_cpu.vhd
124	Holger Lohn's fix for interrupts when 3-state pipeline enabled.	rhoads	7365d 07h	/plasma/trunk/vhdl/mlite_cpu.vhd
120	Make generics "GENERIC"	rhoads	7507d 21h	/plasma/trunk/vhdl/mlite_cpu.vhd
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7546d 08h	/plasma/trunk/vhdl/mlite_cpu.vhd
96	Simplify take_branch	rhoads	8069d 11h	/plasma/trunk/vhdl/mlite_cpu.vhd
83	Updated comments, accurate_timing on by default	rhoads	8071d 05h	/plasma/trunk/vhdl/mlite_cpu.vhd
73	pipeline, better reset	rhoads	8079d 06h	/plasma/trunk/vhdl/mlite_cpu.vhd
60	reset control	rhoads	8087d 11h	/plasma/trunk/vhdl/mlite_cpu.vhd
47	Altera	rhoads	8105d 08h	/plasma/trunk/vhdl/mlite_cpu.vhd
43	Renamed M-lite to Plasma	rhoads	8185d 08h	/plasma/trunk/vhdl/mlite_cpu.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8217d 13h	/plasma/trunk/vhdl/mlite_cpu.vhd

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