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[/] [plasma/] [trunk/] [vhdl/] [mlite_pack.vhd] - Rev 429

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Rev Log message Author Age Path
429 Changed INIT bit length in RAM16X1D and RAM32X1D rhoads 4165d 19h /plasma/trunk/vhdl/mlite_pack.vhd
397 Added RAM32X1D option rhoads 5052d 09h /plasma/trunk/vhdl/mlite_pack.vhd
383 Permit up to 64KB internal RAM and updated cache code. rhoads 5214d 16h /plasma/trunk/vhdl/mlite_pack.vhd
352 linus 5717d 06h /plasma/trunk/vhdl/mlite_pack.vhd
350 root 5746d 01h /plasma/trunk/vhdl/mlite_pack.vhd
346 Support optional 4KB cache rhoads 5813d 20h /plasma/trunk/vhdl/mlite_pack.vhd
332 Updated Altera lpm_ram_dp rhoads 5874d 15h /plasma/trunk/vhdl/mlite_pack.vhd
285 Added eth_dma rhoads 6153d 15h /plasma/trunk/vhdl/mlite_pack.vhd
264 Latch address and byte_we in mem_ctrl.vhd rhoads 6196d 23h /plasma/trunk/vhdl/mlite_pack.vhd
202 Defined outputing PC as stage #0 rhoads 6436d 01h /plasma/trunk/vhdl/mlite_pack.vhd
194 Implemented BREAK and SYSCALL opcodes rhoads 6500d 20h /plasma/trunk/vhdl/mlite_pack.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6846d 13h /plasma/trunk/vhdl/mlite_pack.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7326d 12h /plasma/trunk/vhdl/mlite_pack.vhd
128 Reset all registers, constants now upper case. rhoads 7463d 23h /plasma/trunk/vhdl/mlite_pack.vhd
125 Fixed pc_source_type comment. rhoads 7482d 13h /plasma/trunk/vhdl/mlite_pack.vhd
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7663d 13h /plasma/trunk/vhdl/mlite_pack.vhd
96 Simplify take_branch rhoads 8186d 17h /plasma/trunk/vhdl/mlite_pack.vhd
91 Removed unused alu_function_type entries rhoads 8188d 10h /plasma/trunk/vhdl/mlite_pack.vhd
70 pipeline rhoads 8196d 12h /plasma/trunk/vhdl/mlite_pack.vhd
62 updated LPM functions; mem_none->mem_fetch rhoads 8204d 17h /plasma/trunk/vhdl/mlite_pack.vhd

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