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54 Update benchmarks to work with supervisor spec v1.7 skordal 3327d 10h /potato/branches
53 Upgrade processor core to conform to the supervisor spec v1.7 skordal 3329d 11h /potato/branches
52 Correct .data section of sw-jal test skordal 3329d 11h /potato/branches
51 Add scall/ecall, sbreak/ebreak and timer interrupt tests skordal 3329d 11h /potato/branches
50 Update test environment to the new supervisor ISA skordal 3341d 11h /potato/branches
49 Correct spelling of "privileged" skordal 3351d 10h /potato/branches
48 Create branch for upgrading to the new privileged ISA skordal 3351d 10h /potato/branches
46 Remove branch: cache-playground skordal 3354d 12h /potato/branches
44 Add instruction cache and use the WB adapter as dmem interface skordal 3354d 13h /potato/branches
43 Improve instruction fetch logic skordal 3354d 13h /potato/branches
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3354d 13h /potato/branches
41 Make continouous status register reads asynchronous skordal 3354d 13h /potato/branches
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.		 skordal 3354d 13h /potato/branches
39 Disable IRQs when handling exceptions skordal 3354d 13h /potato/branches
38 Add "Hello World" test application skordal 3354d 14h /potato/branches
37 Add macro to set the TOHOST register from C code skordal 3354d 14h /potato/branches
33 Ensure correct read of CSR after stall skordal 3354d 14h /potato/branches
32 Prevent jumping/branching when stalling skordal 3357d 11h /potato/branches
31 Prevent flushing the pipeline if it is stalling skordal 3357d 12h /potato/branches
30 Add testcase for a combination of instructions that fail when using cache skordal 3359d 17h /potato/branches

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