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[/] [potato/] [trunk/] [example/] [toplevel.vhd] - Rev 43

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Rev Log message Author Age Path
21 Upgrade the example design to use a 60 MHz system clock skordal 3468d 14h /potato/trunk/example/toplevel.vhd
12 Update example design with correct bug-report URL and testbenches skordal 3481d 22h /potato/trunk/example/toplevel.vhd
7 Add test design for the Nexys 4 board from Digilent skordal 3493d 18h /potato/trunk/example/toplevel.vhd

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