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[/] [potato] - Rev 43

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Rev	Log message	Author	Age	Path
43	Improve instruction fetch logic	skordal	3413d 08h	/potato
42	Move check for stall from irq_asserted to exception_taken in EX stage	skordal	3413d 08h	/potato
41	Make continouous status register reads asynchronous	skordal	3413d 08h	/potato
40	Reduce example design clock frequency to 50 MHz - Also includes a minor change to make the address decoder/interconnect work better with burst transfers.	skordal	3413d 08h	/potato
39	Disable IRQs when handling exceptions	skordal	3413d 08h	/potato
38	Add "Hello World" test application	skordal	3413d 09h	/potato
37	Add macro to set the TOHOST register from C code	skordal	3413d 09h	/potato
36	Ensure correct read of CSR after stall	skordal	3413d 09h	/potato
35	Prevent jumping/branching when stalling	skordal	3413d 09h	/potato
34	Prevent flushing the pipeline if it is stalling	skordal	3413d 09h	/potato
33	Ensure correct read of CSR after stall	skordal	3413d 10h	/potato
32	Prevent jumping/branching when stalling	skordal	3416d 07h	/potato
31	Prevent flushing the pipeline if it is stalling	skordal	3416d 08h	/potato
30	Add testcase for a combination of instructions that fail when using cache	skordal	3418d 12h	/potato
29	Add reset functionality for the WB arbiter state machine	skordal	3421d 07h	/potato
28	Add rudimentary User's manual	skordal	3427d 07h	/potato
27	Prevent exceptions from being taken while stalling	skordal	3427d 09h	/potato
26	Prevent exceptions from being taken while stalling Jumping to an exception handler while stalling and waiting for a load/store instruction to finish can cause undefined results from the load/store instruction. This actually fixes the issue mentioned in revision r20.	skordal	3427d 12h	/potato
25	Add placeholder cache modules and a wishbone arbiter	skordal	3429d 16h	/potato
24	Remove unused STRINGIFY macros	skordal	3430d 05h	/potato

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[/] [potato] - Rev 43

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