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Rev Log message Author Age Path
24 New directory structure. root 5579d 08h /r2000/trunk
23 - when freeze or stall; don't let memory operations
- Modification on the CP0
- The CP0 is deplaced in the WB stage
- The INT, SI event signals are treated asynchronously in the WB stage
- The rCAUSE register is asynchronous now
- The wException signal is asyncronous instantanously
- Add a repeat/continous treatement (not completed yet)

- *** The "INT EXCEPTION NO STALL" work correctly		 ameziti 5937d 17h /trunk
22 - Some modifications for testing exception. ameziti 5972d 10h /trunk
21 - Flush must be on all signals in the pipeline. ameziti 5972d 10h /trunk
20 - Modification of CP0 to wait the end of all stalls before to process Exception.
- Set "Exception sign" active until all Stalls are completed.		 ameziti 5972d 17h /trunk
19 - Exception signals must be stalled, flushed, stoped or cleared(except reset)
- Look at 14-07-2007
- except the asynchronous event like "external interruption"		 ameziti 5972d 23h /trunk
18 - Read/Write of the CP0 register is in the WB stage, but Exception detection begin from the MEM stage. ameziti 5973d 00h /trunk
17 - UnFonctional Modifications: Change the name of the address port of "CP0". ameziti 5973d 00h /trunk
16 - Remove All generable files from the project. ameziti 5973d 08h /trunk
15 - UnFonctional Modifications.
- Change the "CP0" define to "EXCEPTION".		 ameziti 5973d 09h /trunk
14 Remove unnecessary files from project. ameziti 5973d 17h /trunk
13 - To simplify the exception traitement: Instruction are executed serialy.
- Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.		 ameziti 5973d 17h /trunk
12 To simplify the exception traitement: Instruction are executed serialy. ameziti 5973d 18h /trunk
11 Exception event must be treated CONCURRENTLY with the other event that stall the pipeline. ameziti 5973d 18h /trunk
10 Modification of the CP0. ameziti 5973d 18h /trunk
9 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.		 ameziti 5973d 18h /trunk
8 Enhancement of the "Controler specification doc". ameziti 5976d 18h /trunk
7 Add Pipeline Controler specification documentation. ameziti 5977d 17h /trunk
6 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.		 ameziti 5977d 19h /trunk
5 Remove the Multiple Arithmetic Unit fonction.
- The Pipeline must stall when Mult/Div unit is busy.
- Whether there's a mflo or mfhi.
- see `define MULTIPLE_ALU		 ameziti 5978d 16h /trunk

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