OpenCores
URL https://opencores.org/ocsvn/raptor64/raptor64/trunk

Subversion Repositories raptor64

[/] [raptor64/] [trunk/] [rtl/] [verilog] - Rev 52

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
52 - most recent updates to
- compiler (thread keyword) , shift bug fix
- CPU segmentation model update
- SimpleMMU added		 robfinch 4169d 12h /raptor64/trunk/rtl/verilog
50 - interrupt work robfinch 4183d 17h /raptor64/trunk/rtl/verilog
48 - fixed pipeline bug
- added segment registers
- updated bootrom		 robfinch 4188d 04h /raptor64/trunk/rtl/verilog
45 - separate exception status per context
- debugging PC
-		 robfinch 4196d 19h /raptor64/trunk/rtl/verilog
44 - fix: assert byte select lines during burst access
- fixup bitfield instructions		 robfinch 4203d 07h /raptor64/trunk/rtl/verilog
42 - updated assembler, sample files, 32 bit ISA robfinch 4207d 13h /raptor64/trunk/rtl/verilog
41 - change to 32 bit ISA robfinch 4207d 13h /raptor64/trunk/rtl/verilog
33 - updated cpu files robfinch 4226d 09h /raptor64/trunk/rtl/verilog
31 - added more smaller modules robfinch 4426d 23h /raptor64/trunk/rtl/verilog
30 - separated out Branch History, regfile, and TLB robfinch 4428d 11h /raptor64/trunk/rtl/verilog
29 - exception processing update robfinch 4431d 07h /raptor64/trunk/rtl/verilog
25 - updated processor robfinch 4441d 06h /raptor64/trunk/rtl/verilog
21 - fixes, loop, instruction buffer robfinch 4454d 03h /raptor64/trunk/rtl/verilog
20 - more source changes robfinch 4458d 08h /raptor64/trunk/rtl/verilog
19 - added instruction buffer for non-icache operation robfinch 4458d 08h /raptor64/trunk/rtl/verilog
16 - working on interrupt hardware robfinch 4459d 07h /raptor64/trunk/rtl/verilog
15 - disassembles opcodes for diagnostic dump robfinch 4460d 00h /raptor64/trunk/rtl/verilog
14 - many changes
- removed cmd bus from sc version
-		 robfinch 4460d 00h /raptor64/trunk/rtl/verilog
13 - single context (sc) version of cpu robfinch 4462d 05h /raptor64/trunk/rtl/verilog
12 - updated for updated instruction set
- added WB ROM		 robfinch 4462d 05h /raptor64/trunk/rtl/verilog

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.