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[/] [raytrac/] [branches/] [fp/] [fadd32.vhd] - Rev 158

Rev	Log message	Author	Age	Path
158	Changing std_logic_vector types to my custom far more convinients xfloat32\!	jguarin2002	4464d 14h	/raytrac/branches/fp/fadd32.vhd
157	For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim	jguarin2002	4465d 02h	/raytrac/branches/fp/fadd32.vhd
155	Changes applied prior to testbenching using the script tb_compiler.py	jguarin2002	4468d 14h	/raytrac/branches/fp/fadd32.vhd
153	last modifications for tb_compiler.py compliance	jguarin2002	4471d 06h	/raytrac/branches/fp/fadd32.vhd
152	Test bench oriented modifications	jguarin2002	4475d 07h	/raytrac/branches/fp/fadd32.vhd
150	First Beta of RayTrac for a total size of 3874 lcells. Great Result\!	jguarin2002	4548d 00h	/raytrac/branches/fp/fadd32.vhd
139	Sync	jguarin2002	4658d 15h	/raytrac/branches/fp/fadd32.vhd
137	Syncing with enables and eleminated all the register outputs since none block should carry on a register output	jguarin2002	4669d 07h	/raytrac/branches/fp/fadd32.vhd
121	taking out std_logic_arith from sight.... no conversions allowed	jguarin2002	4714d 19h	/raytrac/branches/fp/fadd32.vhd
120	Beta 0 Adder LCELLS 373	jguarin2002	4720d 17h	/raytrac/branches/fp/fadd32.vhd
119	382 LEs Adder, RTL viewer Check Ok	jguarin2002	4720d 23h	/raytrac/branches/fp/fadd32.vhd
118	fp beta version reached a 17,5% logic cell starting at 450 LEs and finishing in 371 LEs for fadd32	jguarin2002	4721d 06h	/raytrac/branches/fp/fadd32.vhd