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[/] [raytrac] - Rev 216

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216 At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed jguarin2002 4382d 03h /raytrac
215 At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed jguarin2002 4382d 03h /raytrac
214 At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed jguarin2002 4382d 03h /raytrac
213 Arithpack: changes to suppport the Beta Raytrac RTL description (with almost DMA caps) jguarin2002 4382d 03h /raytrac
212 DPC changes\n\n\t+ established the DCS system rather than the UCA definitively\n\t+ Rather than usign 4 result queues now theres just a single one, of course 4 times wider, this was made to gain simplicity when writing and reading the RTL description that adapts this 4/3/1 word wide result buffer output into a 1 word wide result buffer input\n\t+ Added the Q1 queue to syncrhonize magnitude and normalization ops, managing them to enter at the sime tame rather than different times, formerly it was implemented by setting the normalization and magnitude results into the results buffers at 25th beat and 20th beat respectively, now both results enter into THE SINGLE RESULT QUEUE at 25th beat. This change also forces that Dot product operation to use the Q1 hardware and entering also at beath 25th into the result queue, it could be done in an earlier beatt (in fact in the 19th) but multiplexation logic would have to be added. jguarin2002 4382d 03h /raytrac
211 Raytrac Beta 0.1 with Avalon MM Master & Avalon MM Slave Interfaces. Done\! jguarin2002 4382d 04h /raytrac
210 Document advance..... towards dma oriented raytrac jguarin2002 4393d 16h /raytrac
209 Working towards a DMA oriented RayTRac jguarin2002 4393d 16h /raytrac
208 Working towards a DMA oriented RayTRac jguarin2002 4393d 16h /raytrac
207 Working towards a DMA oriented RayTRac jguarin2002 4393d 16h /raytrac
206 Working towards a DMA oriented RayTRac jguarin2002 4393d 16h /raytrac
205 Working towards a DMA oriented RayTRac jguarin2002 4393d 16h /raytrac
204 Working towards a DMA oriented RayTRac jguarin2002 4393d 16h /raytrac
203 Working towards a DMA oriented RayTRac jguarin2002 4393d 16h /raytrac
202 Working towards a DMA oriented RayTRac jguarin2002 4393d 16h /raytrac
201 files no longer needed im.vhd and fadd32long.vhd jguarin2002 4393d 17h /raytrac
200 raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers jguarin2002 4393d 17h /raytrac
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4409d 23h /raytrac
198 Check out for the best out for the best organization so the datapath does not consume to many logic cells jguarin2002 4409d 23h /raytrac
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4420d 00h /raytrac

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