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URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

[/] [rio/] [trunk] - Rev 52

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Rev Log message Author Age Path
52 Correcting FTYPE_MESSAGE_CLASS constant. magro732 3442d 20h /rio/trunk
49 Moving packet generation API from riostack.c to new file riopacket.c.
The riostack.c is now transparent to all packets and does not answer on its own to maintenance packets. That now has to be handled in the user-written code that instantiates the riostack.
Moving all regression tests into new files test_riostack.c and test_riopacket.c.		 magro732 3455d 02h /rio/trunk
28 Correcting bug in RioSwitch.vhd internal Wishbone interconnect.
Modifying an existing test case in TestRioSwitch.vhd to provoke the error.		 magro732 3588d 06h /rio/trunk
25 Correcting compiler errors in TestRioPcsUart.vhd magro732 3756d 23h /rio/trunk
24 Changing errornous use statement. magro732 3756d 23h /rio/trunk
20 Adding software C-stack and matching VHDL modules. magro732 3938d 19h /rio/trunk
9 Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes) azdem 4028d 06h /rio/trunk
8 Adding signal descriptions in comments. magro732 4071d 19h /rio/trunk
7 Adding missing generic parameters to RioPacketBuffer. magro732 4158d 23h /rio/trunk
6 Adding RioWbBridge. Sorry, no testbench for this one. magro732 4159d 01h /rio/trunk
5 Uploading primitive documentation. magro732 4165d 17h /rio/trunk
4 Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification. magro732 4188d 07h /rio/trunk
3 Adding RioPacketBuffer and testbench. magro732 4188d 23h /rio/trunk
2 Adding RioSwitch and testbench. magro732 4189d 01h /rio/trunk
1 The project and the structure was created root 4190d 07h /rio/trunk

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