URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

[/] [rio] - Rev 25

Rev	Log message	Author	Age	Path
25	Correcting compiler errors in TestRioPcsUart.vhd	magro732	3769d 17h	/rio
24	Changing errornous use statement.	magro732	3769d 17h	/rio
23	Tagging alpha release 2.0.0.	magro732	3886d 11h	/rio
22	Tagging release 1.0.0.	magro732	3886d 11h	/rio
21	Branching of a single symbol version of the new RioSerial.	magro732	3886d 11h	/rio
20	Adding software C-stack and matching VHDL modules.	magro732	3951d 13h	/rio
19	Removing synthesis warnings.	magro732	3976d 13h	/rio
18	Making RioSerial entity the same as before+minor fixes.	magro732	3977d 12h	/rio
17	Removing latch and improving timing.	magro732	3978d 12h	/rio
16	Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing.	magro732	3978d 13h	/rio
15	All testcases are ok. Still needs some tweeks though.	magro732	3982d 14h	/rio
14	Most issues solved, testbench issues remains.	magro732	3985d 13h	/rio
13	Timeouts are working.	magro732	3988d 13h	/rio
12	Backup of recent work, debugging new RioSerial.	magro732	3999d 12h	/rio
11	Receiver ready, transmitter is compiling.	magro732	3999d 13h	/rio
10	Branch to develop support for parallel symbols.	magro732	3999d 13h	/rio
9	Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)	azdem	4041d 01h	/rio
8	Adding signal descriptions in comments.	magro732	4084d 14h	/rio
7	Adding missing generic parameters to RioPacketBuffer.	magro732	4171d 18h	/rio
6	Adding RioWbBridge. Sorry, no testbench for this one.	magro732	4171d 20h	/rio