URL https://opencores.org/ocsvn/rio/rio/trunk

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[/] [rio] - Rev 27

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Rev	Log message	Author	Age	Path
27	Adding missing code to single-symbol pipelined transmitter. Not tested nor copiled.	magro732	3779d 11h	/rio
26	Temporary checkin of parallelSymbols branch. It does not work yet.	magro732	3939d 22h	/rio
25	Correcting compiler errors in TestRioPcsUart.vhd	magro732	3946d 16h	/rio
24	Changing errornous use statement.	magro732	3946d 16h	/rio
23	Tagging alpha release 2.0.0.	magro732	4063d 10h	/rio
22	Tagging release 1.0.0.	magro732	4063d 10h	/rio
21	Branching of a single symbol version of the new RioSerial.	magro732	4063d 10h	/rio
20	Adding software C-stack and matching VHDL modules.	magro732	4128d 12h	/rio
19	Removing synthesis warnings.	magro732	4153d 12h	/rio
18	Making RioSerial entity the same as before+minor fixes.	magro732	4154d 11h	/rio
17	Removing latch and improving timing.	magro732	4155d 11h	/rio
16	Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing.	magro732	4155d 12h	/rio
15	All testcases are ok. Still needs some tweeks though.	magro732	4159d 12h	/rio
14	Most issues solved, testbench issues remains.	magro732	4162d 12h	/rio
13	Timeouts are working.	magro732	4165d 12h	/rio
12	Backup of recent work, debugging new RioSerial.	magro732	4176d 11h	/rio
11	Receiver ready, transmitter is compiling.	magro732	4176d 12h	/rio
10	Branch to develop support for parallel symbols.	magro732	4176d 12h	/rio
9	Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)	azdem	4217d 23h	/rio
8	Adding signal descriptions in comments.	magro732	4261d 13h	/rio

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[/] [rio] - Rev 27

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