URL https://opencores.org/ocsvn/rise/rise/trunk

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[/] [rise/] [trunk/] [vhdl/] [ex_stage.vhd] - Rev 148

Rev	Log message	Author	Age	Path
148	New directory structure.	root	5601d 22h	/rise/trunk/vhdl/ex_stage.vhd
105	- OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT.	cwalter	6385d 05h	/rise/trunk/vhdl/ex_stage.vhd
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6387d 11h	/rise/trunk/vhdl/ex_stage.vhd
97	Fixed bug: only set branch and clear signals if branch is actually executed.	jlechner	6387d 12h	/rise/trunk/vhdl/ex_stage.vhd
96	- SR register is now computed in ALU stage.	cwalter	6387d 12h	/rise/trunk/vhdl/ex_stage.vhd
90	Added output signal for clearing all register locks when a branch instruction is executed. This is necessary because the id stage could have locked registers for an instruction that is cleared out of the pipeline due to the branch.	jlechner	6387d 13h	/rise/trunk/vhdl/ex_stage.vhd
79	- Added barrel shifter.	cwalter	6387d 16h	/rise/trunk/vhdl/ex_stage.vhd
71	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation	jlechner	6388d 03h	/rise/trunk/vhdl/ex_stage.vhd
8	Implementation of execute stage and register lock unit. Some changes im RISE package.	jlechner	6401d 12h	/rise/trunk/vhdl/ex_stage.vhd
2	Initial commit of project	jlechner	6426d 08h	/rise/trunk/vhdl/ex_stage.vhd