URL https://opencores.org/ocsvn/rise/rise/trunk

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[/] [rise/] [trunk/] [vhdl/] [mem_stage.vhd] - Rev 117

Rev	Log message	Author	Age	Path
117	Uart im mem_stage	trinklhar	6447d 09h	/rise/trunk/vhdl/mem_stage.vhd
104	- Added missing signal dmem_data_in.	cwalter	6454d 03h	/rise/trunk/vhdl/mem_stage.vhd
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6456d 09h	/rise/trunk/vhdl/mem_stage.vhd
74	- Fixed bug where register value used by load was passed through to write back. Correct is ALU value.	cwalter	6456d 16h	/rise/trunk/vhdl/mem_stage.vhd
71	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation	jlechner	6457d 01h	/rise/trunk/vhdl/mem_stage.vhd
61	- Applied indenting tool. - Added first basic implementation for testing.	cwalter	6457d 05h	/rise/trunk/vhdl/mem_stage.vhd
52	- stall_out must be initialized to '0'	cwalter	6457d 09h	/rise/trunk/vhdl/mem_stage.vhd
38	Memory output signal is now passed on asynchronously to write back stage.	jlechner	6458d 06h	/rise/trunk/vhdl/mem_stage.vhd
2	Initial commit of project	jlechner	6495d 06h	/rise/trunk/vhdl/mem_stage.vhd