URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [rise.vhd] - Rev 58

Rev	Log message	Author	Age	Path
58	- lr_enable signal in component wb_state should have direction out.	cwalter	6516d 15h	/rise/trunk/vhdl/rise.vhd
39	- Added wr_enable signals for imem and dmem - Changed signals for register lock unit (this concerns id-stage and write-back-stage)	jlechner	6517d 14h	/rise/trunk/vhdl/rise.vhd
27	Added new register write enable signals to component instantiation of register_file and wb_stage.	jlechner	6519d 10h	/rise/trunk/vhdl/rise.vhd
16	- Added second register locking port reg_lock1 to RLU.	cwalter	6524d 13h	/rise/trunk/vhdl/rise.vhd
2	Initial commit of project	jlechner	6554d 14h	/rise/trunk/vhdl/rise.vhd