URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [rise_pack.vhd] - Rev 151

Rev	Log message	Author	Age	Path
151	Started to include generic VHDL description of memories.	jlechner	5241d 18h	/rise/trunk/vhdl/rise_pack.vhd
148	New directory structure.	root	5578d 05h	/rise/trunk/vhdl/rise_pack.vhd
126	Added constant for cpu frequency (needed for UART)	trinklhar	6353d 23h	/rise/trunk/vhdl/rise_pack.vhd
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6354d 00h	/rise/trunk/vhdl/rise_pack.vhd
118	insert Uart address constant	trinklhar	6354d 19h	/rise/trunk/vhdl/rise_pack.vhd
70	Moved opcode and conditional constants and opcode_t and cond_t data types to rise_const_pack.vhd.	jlechner	6364d 11h	/rise/trunk/vhdl/rise_pack.vhd
53	- Removed unused constant COND_NONE.	cwalter	6364d 18h	/rise/trunk/vhdl/rise_pack.vhd
46	- Added constant for RESET_VECTOR.	cwalter	6364d 23h	/rise/trunk/vhdl/rise_pack.vhd
40	- Added seperate memory output vector to MEM_WB_REGISTER. - Added status register to MEM_WB_REGISTER.	jlechner	6365d 15h	/rise/trunk/vhdl/rise_pack.vhd
31	- Added PC_RESET_VECTOR constant.	cwalter	6365d 17h	/rise/trunk/vhdl/rise_pack.vhd
12	- Added constant definitions for SR, PC and LR register.	cwalter	6375d 12h	/rise/trunk/vhdl/rise_pack.vhd
8	Implementation of execute stage and register lock unit. Some changes im RISE package.	jlechner	6377d 19h	/rise/trunk/vhdl/rise_pack.vhd
5	- correct register address width is 4 bit and not 5 bit. - added constants for OPCODES, COND and SR.	cwalter	6396d 12h	/rise/trunk/vhdl/rise_pack.vhd
2	Initial commit of project	jlechner	6402d 16h	/rise/trunk/vhdl/rise_pack.vhd