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[/] [rise/] [trunk/] [vhdl/] [wb_stage.vhd] - Rev 151

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Rev Log message Author Age Path
148 New directory structure. root 5589d 18h /rise/trunk/vhdl/wb_stage.vhd
122 Removed UART again again trinklhar 6365d 12h /rise/trunk/vhdl/wb_stage.vhd
119 Uart wieder ausgebaut trinklhar 6366d 07h /rise/trunk/vhdl/wb_stage.vhd
116 writes to uart when write to reg 0 trinklhar 6367d 14h /rise/trunk/vhdl/wb_stage.vhd
114 Uart 0.3 trinklhar 6369d 08h /rise/trunk/vhdl/wb_stage.vhd
113 Uart reset funkt trinklhar 6369d 09h /rise/trunk/vhdl/wb_stage.vhd
112 Uart drin aber signale nicht eingebunden trinklhar 6369d 10h /rise/trunk/vhdl/wb_stage.vhd
106 - ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT. cwalter 6373d 01h /rise/trunk/vhdl/wb_stage.vhd
95 - Write back now only updates SR in case of a LOAD. cwalter 6375d 08h /rise/trunk/vhdl/wb_stage.vhd
91 - Computed new SR values from ALU result. cwalter 6375d 09h /rise/trunk/vhdl/wb_stage.vhd
83 - sr_enable and lr_enable where incorrect. cwalter 6375d 12h /rise/trunk/vhdl/wb_stage.vhd
76 - Changed order of some statements to improve readability. cwalter 6375d 12h /rise/trunk/vhdl/wb_stage.vhd
71 Added RISE_PACK_SPECIFIC containing either
- constants declarations for synthesis or
- enumeration types for simulation		 jlechner 6375d 23h /rise/trunk/vhdl/wb_stage.vhd
61 - Applied indenting tool.
- Added first basic implementation for testing.		 cwalter 6376d 04h /rise/trunk/vhdl/wb_stage.vhd
55 - clear_out must be initialized to '0'. cwalter 6376d 07h /rise/trunk/vhdl/wb_stage.vhd
43 Correct implementation of necessary unlocking signals that are conncted to register locking unit. jlechner 6377d 04h /rise/trunk/vhdl/wb_stage.vhd
28 Added new register write enable signals. jlechner 6379d 00h /rise/trunk/vhdl/wb_stage.vhd
2 Initial commit of project jlechner 6414d 04h /rise/trunk/vhdl/wb_stage.vhd

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