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[/] [robust_axi_fabric/] [trunk/] [src/] [base] - Rev 23

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Rev Log message Author Age Path
23 revision 1.5 eyalhoc 4731d 10h /robust_axi_fabric/trunk/src/base
22 eyalhoc 4743d 10h /robust_axi_fabric/trunk/src/base
21 fixed pending also for slave fifos eyalhoc 4744d 09h /robust_axi_fabric/trunk/src/base
20 IC give WVALID before AWREADY eyalhoc 4747d 03h /robust_axi_fabric/trunk/src/base
19 IC support same ID from different masters eyalhoc 4750d 10h /robust_axi_fabric/trunk/src/base
18 RobustVerilog version 1.4 compatible eyalhoc 4751d 02h /robust_axi_fabric/trunk/src/base
17 Support RobustVerilog project eyalhoc 4763d 11h /robust_axi_fabric/trunk/src/base
16 GUI support eyalhoc 4770d 06h /robust_axi_fabric/trunk/src/base
15 eyalhoc 4779d 06h /robust_axi_fabric/trunk/src/base
13 support single slave eyalhoc 4796d 12h /robust_axi_fabric/trunk/src/base
12 allow no user signals eyalhoc 4801d 15h /robust_axi_fabric/trunk/src/base
11 use match signals eyalhoc 4801d 15h /robust_axi_fabric/trunk/src/base
9 fixed bug in address decoder eyalhoc 4820d 08h /robust_axi_fabric/trunk/src/base
8 fixed bug in address decoding
if decode error without decode error slave mux to last slave
eyalhoc 4821d 07h /robust_axi_fabric/trunk/src/base
7 added header eyalhoc 4822d 13h /robust_axi_fabric/trunk/src/base
3 default definition file changed to create only 1 fabric eyalhoc 4833d 01h /robust_axi_fabric/trunk/src/base
2 initial upload of files eyalhoc 4833d 07h /robust_axi_fabric/trunk/src/base

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