URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Rev 35

Rev	Log message	Author	Age	Path
35	- several bug fixes - mul,mod,div immediates mode than 8 bits - page two opcode fix on cache miss - setting upper pc bits in emulation mode (store)	robfinch	3884d 05h	/rtf65002/trunk/rtl/verilog/cache_controller.v
32	- many changes - new instructions - code reorganization	robfinch	3894d 19h	/rtf65002/trunk/rtl/verilog/cache_controller.v
30	- added additional branches - modified the pc increment - modified interrupts, all vector through BRK - registered some decodes - added SUPPORT macros to allow core trimming	robfinch	3904d 17h	/rtf65002/trunk/rtl/verilog/cache_controller.v
21	- config processor mode on reset - D flag flags extended precision for add/sub - added software interrupt call facility - unimplmented opcode vectoring - bus error signal support - merge load states to reduce core size - zero out ir during interrupt	robfinch	3919d 12h	/rtf65002/trunk/rtl/verilog/cache_controller.v
20	- greater separation of emulation and native mode in source code - fix instruction buffer fetch for non-cached accesses - fix the sta (d),y instruction	robfinch	3920d 18h	/rtf65002/trunk/rtl/verilog/cache_controller.v
10	- fix rind mode in 32 bit mode - fix flag update in 32 bit mode for RR instructions - initialize cache tags - added flag to disable ints until after sp load	robfinch	3925d 22h	/rtf65002/trunk/rtl/verilog/cache_controller.v
5	setting up project	robfinch	3929d 05h	/rtf65002/trunk/rtl/verilog/cache_controller.v