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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [decode.v] - Rev 38

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Rev	Log message	Author	Age	Path
38	- updated to support the 65c816 opcodes	robfinch	3705d 22h	/rtf65002/trunk/rtl/verilog/decode.v
36	- missing TRB/TSB instructions in 32 bit mode added	robfinch	3854d 17h	/rtf65002/trunk/rtl/verilog/decode.v
35	- several bug fixes - mul,mod,div immediates mode than 8 bits - page two opcode fix on cache miss - setting upper pc bits in emulation mode (store)	robfinch	3901d 10h	/rtf65002/trunk/rtl/verilog/decode.v
32	- many changes - new instructions - code reorganization	robfinch	3912d 00h	/rtf65002/trunk/rtl/verilog/decode.v
30	- added additional branches - modified the pc increment - modified interrupts, all vector through BRK - registered some decodes - added SUPPORT macros to allow core trimming	robfinch	3921d 22h	/rtf65002/trunk/rtl/verilog/decode.v
25	- add EXEC and ATNI instructions - fix store byte zero page indexed - fix break instruction	robfinch	3929d 00h	/rtf65002/trunk/rtl/verilog/decode.v
23	- added subtract immediate from sp - added stack relative addressing mode - added move positive, move negative instructions - fix: TSA instruction	robfinch	3934d 21h	/rtf65002/trunk/rtl/verilog/decode.v
21	- config processor mode on reset - D flag flags extended precision for add/sub - added software interrupt call facility - unimplmented opcode vectoring - bus error signal support - merge load states to reduce core size - zero out ir during interrupt	robfinch	3936d 17h	/rtf65002/trunk/rtl/verilog/decode.v
20	- greater separation of emulation and native mode in source code - fix instruction buffer fetch for non-cached accesses - fix the sta (d),y instruction	robfinch	3937d 23h	/rtf65002/trunk/rtl/verilog/decode.v

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