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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002d.v] - Rev 35

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Rev	Log message	Author	Age	Path
35	- several bug fixes - mul,mod,div immediates mode than 8 bits - page two opcode fix on cache miss - setting upper pc bits in emulation mode (store)	robfinch	3883d 23h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
32	- many changes - new instructions - code reorganization	robfinch	3894d 13h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
30	- added additional branches - modified the pc increment - modified interrupts, all vector through BRK - registered some decodes - added SUPPORT macros to allow core trimming	robfinch	3904d 11h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
25	- add EXEC and ATNI instructions - fix store byte zero page indexed - fix break instruction	robfinch	3911d 13h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
23	- added subtract immediate from sp - added stack relative addressing mode - added move positive, move negative instructions - fix: TSA instruction	robfinch	3917d 11h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
21	- config processor mode on reset - D flag flags extended precision for add/sub - added software interrupt call facility - unimplmented opcode vectoring - bus error signal support - merge load states to reduce core size - zero out ir during interrupt	robfinch	3919d 06h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
20	- greater separation of emulation and native mode in source code - fix instruction buffer fetch for non-cached accesses - fix the sta (d),y instruction	robfinch	3920d 12h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
19	- added multibit shifts - added eight bit CMP instruction	robfinch	3921d 10h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
13	- fix overflow in immediate mode - fix bit instruction N,V setting - add vector base register, modified interrupt vectoring	robfinch	3922d 11h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
12	- added LFSR and TICK count special registers - added MUL/DIV/MOD instructions	robfinch	3923d 11h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
10	- fix rind mode in 32 bit mode - fix flag update in 32 bit mode for RR instructions - initialize cache tags - added flag to disable ints until after sp load	robfinch	3925d 16h	/rtf65002/trunk/rtl/verilog/rtf65002d.v
5	setting up project	robfinch	3928d 23h	/rtf65002/trunk/rtl/verilog/rtf65002d.v

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