URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [rtl/] [cpu/] [zipcpu.v] - Rev 51

Rev	Log message	Author	Age	Path
51	Latest RTL changes, adding 20 cycles/instruction to CPU	dgisselq	2797d 23h	/s6soc/trunk/rtl/cpu/zipcpu.v
46	Added missing files from the 8b branch, deleted unneeded files	dgisselq	2817d 00h	/s6soc/trunk/rtl/cpu/zipcpu.v
30	Brings the CPU up to date with the rest of the ZipCPU distribution.	dgisselq	3115d 13h	/s6soc/trunk/rtl/cpu/zipcpu.v
23	Fixed a bug which caused every instruction to be loaded/prefetched twice.	dgisselq	3120d 00h	/s6soc/trunk/rtl/cpu/zipcpu.v
16	Bug fix. This release fixes several bugs associated with transitioning from user mode to supervisor mode while running from flash memory. This also rewires TIMER-B into a watch-dog timer, and adjusts the LED's to be an indicator of interrupts and whether or not the CPU has stalled or not as well.	dgisselq	3123d 23h	/s6soc/trunk/rtl/cpu/zipcpu.v
11	Runs on hardware now! Added proper pinouts, pipelined wishbone command interface sufficient for loading the flash, a loader to load the flash, and verified that they work.	dgisselq	3131d 12h	/s6soc/trunk/rtl/cpu/zipcpu.v
7	Created/added an initial specification. Updated/corrected several copywrite notices.	dgisselq	3137d 04h	/s6soc/trunk/rtl/cpu/zipcpu.v
2	The initial check in--all the files that will make this SoC work.	dgisselq	3168d 18h	/s6soc/trunk/rtl/cpu/zipcpu.v