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[/] [s6soc/] [trunk/] [rtl] - Rev 16

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16 Bug fix. This release fixes several bugs associated with transitioning from
user mode to supervisor mode while running from flash memory. This also
rewires TIMER-B into a watch-dog timer, and adjusts the LED's to be an
indicator of interrupts and whether or not the CPU has stalled or not as well.		 dgisselq 2965d 03h /s6soc/trunk/rtl
13 Fixed a nasty parameter problem between toplevel and txuart. The UART
transmitter now both works (again), and properly generates the required
interrupts. This also finishes the fixes to the alternate toplevel file,
alttop.v, that should've been fixed in the last release.		 dgisselq 2970d 21h /s6soc/trunk/rtl
12 The UART and PWM audio now work. This includes the changes to make that
happen, as well as the source code for some UART and PWM demo programs.		 dgisselq 2971d 18h /s6soc/trunk/rtl
11 Runs on hardware now! Added proper pinouts, pipelined wishbone command
interface sufficient for loading the flash, a loader to load the flash,
and verified that they work.		 dgisselq 2972d 16h /s6soc/trunk/rtl
8 First pseudo-running version. The alternate configuration (not the main one)
has been initially tested. wbregs works for reading/writing registers,
so it is now possible to test the peripherals.		 dgisselq 2977d 17h /s6soc/trunk/rtl
7 Created/added an initial specification. Updated/corrected several copywrite
notices.		 dgisselq 2978d 08h /s6soc/trunk/rtl
5 These two are my first attempt(s) at a secondary project file, one that can
run as an alternate to the main file but that gives more access to the hardware,
such as programming access to the flash.		 dgisselq 2999d 03h /s6soc/trunk/rtl
4 Lots of updates, as part of actually making this work on hardware. Not there
yet, so this is still pre-alpha.		 dgisselq 2999d 03h /s6soc/trunk/rtl
3 Updated date. dgisselq 2999d 03h /s6soc/trunk/rtl
2 The initial check in--all the files that will make this SoC work. dgisselq 3009d 22h /s6soc/trunk/rtl

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