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[/] [sdhc-sc-core/] [trunk/] [grpSd/] [unitSdWbSlave/] [src/] [SdWbSlave-Rtl-a.vhdl] - Rev 185

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185 Restructuring as source repository: Moved sources out of src subdirectory. rkastl 4908d 16h /sdhc-sc-core/trunk/grpSd/unitSdWbSlave/src/SdWbSlave-Rtl-a.vhdl
171 Worked on wishbone part of thesis.

Refs #37.
Refs #39.
rkastl 4911d 10h /SdWbSlave-Rtl-a.vhdl
170 License rewritten to BSD rkastl 4911d 10h /SdWbSlave-Rtl-a.vhdl
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW
rkastl 4911d 10h /SdWbSlave-Rtl-a.vhdl
164 Headers updated (LGPL, consistent format) rkastl 4911d 10h /SdWbSlave-Rtl-a.vhdl
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.
rkastl 4911d 10h /SdWbSlave-Rtl-a.vhdl
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.
rkastl 4911d 11h /SdWbSlave-Rtl-a.vhdl
123 Write: Must be able to halt SdClk, rest is done. rkastl 4911d 11h /SdWbSlave-Rtl-a.vhdl
122 SdController: Initial read support rkastl 4911d 14h /SdWbSlave-Rtl-a.vhdl
120 SdWbSlave: ClassicRead and ClassicWrite work rkastl 4911d 14h /SdWbSlave-Rtl-a.vhdl
119 SdWb: Synchronization of operation to SdController done, but needs
testing.
rkastl 4911d 14h /SdWbSlave-Rtl-a.vhdl

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