URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [grpSd/] [unitSdWbSlave/] [src/] [SdWbSlave-Rtl-a.vhdl] - Rev 185

Rev	Log message	Author	Age	Path
185	Restructuring as source repository: Moved sources out of src subdirectory.	rkastl	4917d 12h	/sdhc-sc-core/trunk/grpSd/unitSdWbSlave/src/SdWbSlave-Rtl-a.vhdl
171	Worked on wishbone part of thesis. Refs #37. Refs #39.	rkastl	4920d 06h	/SdWbSlave-Rtl-a.vhdl
170	License rewritten to BSD	rkastl	4920d 06h	/SdWbSlave-Rtl-a.vhdl
167	Read+Modify+Write works on HW + Fixed CRC status token (not mentioned in simplified spec) + Improved TestWbMaster to RMW	rkastl	4920d 06h	/SdWbSlave-Rtl-a.vhdl
164	Headers updated (LGPL, consistent format)	rkastl	4920d 06h	/SdWbSlave-Rtl-a.vhdl
160	Verification: Full random read and write single blocks sequence works with checks. Checking the CRC in the card model is missing. Writing at addresses above the card size is missing. Erasing is missing.	rkastl	4920d 06h	/SdWbSlave-Rtl-a.vhdl
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4920d 06h	/SdWbSlave-Rtl-a.vhdl
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4920d 06h	/SdWbSlave-Rtl-a.vhdl
122	SdController: Initial read support	rkastl	4920d 10h	/SdWbSlave-Rtl-a.vhdl
120	SdWbSlave: ClassicRead and ClassicWrite work	rkastl	4920d 10h	/SdWbSlave-Rtl-a.vhdl
119	SdWb: Synchronization of operation to SdController done, but needs testing.	rkastl	4920d 10h	/SdWbSlave-Rtl-a.vhdl