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[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdVerificationTestbench/] [sim] - Rev 184

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Rev Log message Author Age Path
184 Removed WbSlave shell (refs #69)
Moved verification sources to grpSdVerification (fixes #70)		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
178 Fixed regression:
Testbenches did not support synchronous reset.		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
176 Thesis:
Conclusion

Fixes #53,#61.		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
170 License rewritten to BSD rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
164 Headers updated (LGPL, consistent format) rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
161 Verification:
CardModel: Check CRC on received data		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
158 Verification:
Work on Checking
Functional coverage		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
157 Verification:
Testcase with Reads works but Verification not completly
implemented.		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
153 SdVerification:
further development, not done by far		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
147 Sd-Core:
+ Added checking of Busy signal after write		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
136 SDHC:
- SdData refactored to use a single counter
- TestWbMaster added to TbdSd (not functional yet)		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
125 Write works in simulation rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
124 Write: SdClk is disabled, if no data is available. rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
123 Write: Must be able to halt SdClk, rest is done. rkastl 4958d 15h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
122 SdController: Initial read support rkastl 4958d 19h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
113 Read with single block works on cards, but not in simulation. SdData.sv
sends data with one "XXXX" cycle right before the crc.		 rkastl 4958d 19h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
111 Sclk moved to neg. edge -> setup and hold times for fast mode are easier
to reach. (only micro sd does not work in fast mode).		 rkastl 4958d 19h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim
109 Added a data ram. rkastl 4958d 19h /sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim

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