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Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdVerificationTestbench/] [src] - Rev 184

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Rev	Log message	Author	Age	Path
184	Removed WbSlave shell (refs #69) Moved verification sources to grpSdVerification (fixes #70)	rkastl	4995d 18h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
170	License rewritten to BSD	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
165	Only use synchronous high active reset in SDHC-SC-Core.	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
164	Headers updated (LGPL, consistent format)	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
160	Verification: Full random read and write single blocks sequence works with checks. Checking the CRC in the card model is missing. Writing at addresses above the card size is missing. Erasing is missing.	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
158	Verification: Work on Checking Functional coverage	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
157	Verification: Testcase with Reads works but Verification not completly implemented.	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
156	SdVerification: + Split a SdCoreTransaction into multiple WbTransactions: Proof of Concept with a ReadSingleBlock-Transaction + Finish after certain amount of time and present simulation result	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
153	SdVerification: further development, not done by far	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
151	Verification: + redesign: not functional yet	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
150	Testbed: + Simulation made possible + Write works - Sometimes the alignment in the block is not right	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
148	SdVerification: + CardModel: Execution thread which starts initialization and then receives token and parses them. TbdSd: + Added SdWbSdSynchronization.	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
145	Verification: + SdCardModel and SdBFM seperated	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
135	Multiple-Inclusion-Protection to SystemVerilog files added Stops using relative paths in `includes. instead +incdir has to be used.	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
125	Write works in simulation	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
124	Write: SdClk is disabled, if no data is available.	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4995d 19h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
122	SdController: Initial read support	rkastl	4995d 23h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src
111	Sclk moved to neg. edge -> setup and hold times for fast mode are easier to reach. (only micro sd does not work in fast mode).	rkastl	4995d 23h	/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src

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Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitSdVerificationTestbench/] [src] - Rev 184

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