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[/] [sdhc-sc-core/] [trunk/] [src] - Rev 133

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133 SdData: Further refactoring rkastl 4953d 11h /sdhc-sc-core/trunk/src
132 SdData: Refactoring, not done.
Testbench works again, but does not really test anything.		 rkastl 4953d 11h /sdhc-sc-core/trunk/src
130 SdClockMaster: Formal verification rkastl 4953d 11h /sdhc-sc-core/trunk/src
129 SdClockMaster: Redesigned, not finished. Tb with PSL assertions. rkastl 4953d 11h /sdhc-sc-core/trunk/src
128 Sim: Support for psl files added. rkastl 4953d 11h /sdhc-sc-core/trunk/src
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4953d 11h /sdhc-sc-core/trunk/src
125 Write works in simulation rkastl 4953d 11h /sdhc-sc-core/trunk/src
124 Write: SdClk is disabled, if no data is available. rkastl 4953d 11h /sdhc-sc-core/trunk/src
123 Write: Must be able to halt SdClk, rest is done. rkastl 4953d 11h /sdhc-sc-core/trunk/src
122 SdController: Initial read support rkastl 4953d 15h /sdhc-sc-core/trunk/src
121 SdWbSlave inserted into SdTop. SdController does not use it yet. rkastl 4953d 15h /sdhc-sc-core/trunk/src
120 SdWbSlave: ClassicRead and ClassicWrite work rkastl 4953d 15h /sdhc-sc-core/trunk/src
119 SdWb: Synchronization of operation to SdController done, but needs
testing.		 rkastl 4953d 15h /sdhc-sc-core/trunk/src
118 EdgeDetector added. rkastl 4953d 15h /sdhc-sc-core/trunk/src
117 Removed unused units. rkastl 4953d 15h /sdhc-sc-core/trunk/src
116 Wishbone interface for sd core started rkastl 4953d 15h /sdhc-sc-core/trunk/src
115 WbSlave: New header. rkastl 4953d 15h /sdhc-sc-core/trunk/src
114 Read works with model too. rkastl 4953d 15h /sdhc-sc-core/trunk/src
113 Read with single block works on cards, but not in simulation. SdData.sv
sends data with one "XXXX" cycle right before the crc.		 rkastl 4953d 15h /sdhc-sc-core/trunk/src
112 Save wide mode with out gHighSpeedMode = true rkastl 4953d 15h /sdhc-sc-core/trunk/src

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