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[/] [sdhc-sc-core/] [trunk/] [src] - Rev 146

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Rev	Log message	Author	Age	Path
146	SdClockMaster: + fixed output of data at negedge of sclk in high speed mode	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
145	Verification: + SdCardModel and SdBFM seperated	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
144	Simulation files for tbTbdSd created. tbTbdSd is not done and TestWbMaster seems to be lost.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
140	Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete verification tb anyway.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
139	Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in the complete verification environment anyway.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
138	Removed testbench for unitSdCmd because it was a weak testbench and the functionality is tested in the SdVerificationTestbench anyway.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
137	Regression test suite: Removed unneeded testbenches from the makefile. Only complete reusable blocks are tested from now on.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
136	SDHC: - SdData refactored to use a single counter - TestWbMaster added to TbdSd (not functional yet)	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
135	Multiple-Inclusion-Protection to SystemVerilog files added Stops using relative paths in `includes. instead +incdir has to be used.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
134	SdData: Further refactoring.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
133	SdData: Further refactoring	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
132	SdData: Refactoring, not done. Testbench works again, but does not really test anything.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
130	SdClockMaster: Formal verification	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
129	SdClockMaster: Redesigned, not finished. Tb with PSL assertions.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
128	Sim: Support for psl files added.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
125	Write works in simulation	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
124	Write: SdClk is disabled, if no data is available.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4953d 08h	/sdhc-sc-core/trunk/src
122	SdController: Initial read support	rkastl	4953d 11h	/sdhc-sc-core/trunk/src

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[/] [sdhc-sc-core/] [trunk/] [src] - Rev 146

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