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[/] [sdhc-sc-core/] [trunk] - Rev 178

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178 Fixed regression:
Testbenches did not support synchronous reset.		 rkastl 4936d 22h /sdhc-sc-core/trunk
177 Split SdTop into SdClkDomain and SdTop. Refs #60. rkastl 4936d 22h /sdhc-sc-core/trunk
176 Thesis:
Conclusion

Fixes #53,#61.		 rkastl 4936d 22h /sdhc-sc-core/trunk
175 Thesis:

Fixes #45.		 rkastl 4936d 22h /sdhc-sc-core/trunk
174 Thesis:
System integration

Fixes #51.		 rkastl 4936d 22h /sdhc-sc-core/trunk
173 Thesis:
Started with SdController description.

Refs #38.		 rkastl 4936d 22h /sdhc-sc-core/trunk
172 Thesis:
wbclockdomain: refactored and finished.

Fixes #39.		 rkastl 4936d 22h /sdhc-sc-core/trunk
171 Worked on wishbone part of thesis.

Refs #37.
Refs #39.		 rkastl 4936d 22h /sdhc-sc-core/trunk
170 License rewritten to BSD rkastl 4936d 22h /sdhc-sc-core/trunk
169 +sdc file for timing analysis rkastl 4936d 22h /sdhc-sc-core/trunk
168 TbdSd synthesis script reaches timing constraints. rkastl 4936d 22h /sdhc-sc-core/trunk
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW		 rkastl 4936d 22h /sdhc-sc-core/trunk
166 tbTbdSd: fixed rkastl 4936d 22h /sdhc-sc-core/trunk
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4936d 22h /sdhc-sc-core/trunk
164 Headers updated (LGPL, consistent format) rkastl 4936d 22h /sdhc-sc-core/trunk
163 Header-Skript supports writing to file and infile replacement. rkastl 4936d 22h /sdhc-sc-core/trunk
162 Script for generating headers created. rkastl 4936d 22h /sdhc-sc-core/trunk
161 Verification:
CardModel: Check CRC on received data		 rkastl 4936d 22h /sdhc-sc-core/trunk
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4936d 22h /sdhc-sc-core/trunk
159 Verification:
Further work: Checking RAM Actions and reading data is still
missing		 rkastl 4936d 22h /sdhc-sc-core/trunk

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