URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 73

Rev	Log message	Author	Age	Path
73	sdram bug in FPGA mode + 8/16 bit address map fix	dinesha	1212d 01h	/sdr_ctrl/trunk
72	Command Clean up for model-sim mode	dinesha	4205d 09h	/sdr_ctrl/trunk
71	Warning cleanup	dinesha	4257d 01h	/sdr_ctrl/trunk
70	Warning Cleanup	dinesha	4257d 01h	/sdr_ctrl/trunk
69	SDRAM address bit increased from 12 bit to 13 bit	dinesha	4257d 03h	/sdr_ctrl/trunk
68	SDRAM Address bit increased from 12 bit to 13 bit	dinesha	4257d 03h	/sdr_ctrl/trunk
67	time scale removed	dinesha	4327d 01h	/sdr_ctrl/trunk
66	dwm tw, bl paramter are passed on the wb2sdrc module	dinesha	4575d 02h	/sdr_ctrl/trunk
65	Updated Log file with CAS latency support 4,5	dinesha	4575d 10h	/sdr_ctrl/trunk
64	CAS Latency support added for 4,5	dinesha	4575d 10h	/sdr_ctrl/trunk
63	FPGA Bench mark results are added	dinesha	4694d 09h	/sdr_ctrl/trunk
62	Synthesis constraint for simplify	dinesha	4694d 09h	/sdr_ctrl/trunk
61	RTL file list are added into SVN	dinesha	4694d 09h	/sdr_ctrl/trunk
60	warning cleanup	dinesha	4694d 10h	/sdr_ctrl/trunk
59	Control path request and data are register now for better FPGA timing	dinesha	4694d 10h	/sdr_ctrl/trunk
58	Read Data is register on RD_FAST=0 case	dinesha	4694d 10h	/sdr_ctrl/trunk
57	Synthesis constraints are added	dinesha	4695d 00h	/sdr_ctrl/trunk
56	FPGA Synth optimisation	dinesha	4695d 01h	/sdr_ctrl/trunk
55	FPGA Synthesis timing optimisation	dinesha	4695d 01h	/sdr_ctrl/trunk
54	FPGA Timing Optimisation	dinesha	4697d 23h	/sdr_ctrl/trunk