URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core] - Rev 37

Rev	Log message	Author	Age	Path
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4521d 07h	/sdr_ctrl/trunk/rtl/core
36	Clean up	dinesha	4521d 22h	/sdr_ctrl/trunk/rtl/core
33	clean up	dinesha	4522d 00h	/sdr_ctrl/trunk/rtl/core
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4523d 23h	/sdr_ctrl/trunk/rtl/core
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4526d 03h	/sdr_ctrl/trunk/rtl/core
16	8 Bit SDRAM Support is added	dinesha	4527d 22h	/sdr_ctrl/trunk/rtl/core
15	Port cleanup	dinesha	4530d 23h	/sdr_ctrl/trunk/rtl/core
13	column bit are made progrmmable	dinesha	4530d 23h	/sdr_ctrl/trunk/rtl/core
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4535d 00h	/sdr_ctrl/trunk/rtl/core
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4535d 21h	/sdr_ctrl/trunk/rtl/core
3	SDRAM controller core files are checked in	dinesha	4542d 08h	/sdr_ctrl/trunk/rtl/core