URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl/] [core] - Rev 50

Rev	Log message	Author	Age	Path
50	Bug fix the request length is fixe	dinesha	4512d 23h	/sdr_ctrl/trunk/rtl/core
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4513d 22h	/sdr_ctrl/trunk/rtl/core
46	test bench upgrade + rtl cleanup	dinesha	4515d 23h	/sdr_ctrl/trunk/rtl/core
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4516d 03h	/sdr_ctrl/trunk/rtl/core
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4518d 01h	/sdr_ctrl/trunk/rtl/core
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4520d 05h	/sdr_ctrl/trunk/rtl/core
36	Clean up	dinesha	4520d 20h	/sdr_ctrl/trunk/rtl/core
33	clean up	dinesha	4520d 22h	/sdr_ctrl/trunk/rtl/core
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4522d 21h	/sdr_ctrl/trunk/rtl/core
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4525d 01h	/sdr_ctrl/trunk/rtl/core
16	8 Bit SDRAM Support is added	dinesha	4526d 20h	/sdr_ctrl/trunk/rtl/core
15	Port cleanup	dinesha	4529d 20h	/sdr_ctrl/trunk/rtl/core
13	column bit are made progrmmable	dinesha	4529d 21h	/sdr_ctrl/trunk/rtl/core
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4533d 21h	/sdr_ctrl/trunk/rtl/core
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4534d 19h	/sdr_ctrl/trunk/rtl/core
3	SDRAM controller core files are checked in	dinesha	4541d 05h	/sdr_ctrl/trunk/rtl/core