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[/] [sdr_ctrl/] [trunk/] [rtl/] [core] - Rev 69

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Rev Log message Author Age Path
69 SDRAM address bit increased from 12 bit to 13 bit dinesha 4129d 04h /sdr_ctrl/trunk/rtl/core
64 CAS Latency support added for 4,5 dinesha 4447d 11h /sdr_ctrl/trunk/rtl/core
55 FPGA Synthesis timing optimisation dinesha 4567d 03h /sdr_ctrl/trunk/rtl/core
54 FPGA Timing Optimisation dinesha 4570d 01h /sdr_ctrl/trunk/rtl/core
51 FPGA relating timing optimisation done dinesha 4571d 01h /sdr_ctrl/trunk/rtl/core
50 Bug fix the request length is fixe dinesha 4573d 05h /sdr_ctrl/trunk/rtl/core
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4574d 04h /sdr_ctrl/trunk/rtl/core
46 test bench upgrade + rtl cleanup dinesha 4576d 05h /sdr_ctrl/trunk/rtl/core
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4576d 09h /sdr_ctrl/trunk/rtl/core
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4578d 07h /sdr_ctrl/trunk/rtl/core
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4580d 11h /sdr_ctrl/trunk/rtl/core
36 Clean up dinesha 4581d 02h /sdr_ctrl/trunk/rtl/core
33 clean up dinesha 4581d 04h /sdr_ctrl/trunk/rtl/core
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4583d 03h /sdr_ctrl/trunk/rtl/core
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4585d 07h /sdr_ctrl/trunk/rtl/core
16 8 Bit SDRAM Support is added dinesha 4587d 02h /sdr_ctrl/trunk/rtl/core
15 Port cleanup dinesha 4590d 02h /sdr_ctrl/trunk/rtl/core
13 column bit are made progrmmable dinesha 4590d 03h /sdr_ctrl/trunk/rtl/core
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4594d 03h /sdr_ctrl/trunk/rtl/core
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4595d 01h /sdr_ctrl/trunk/rtl/core

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