URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl] - Rev 40

Rev	Log message	Author	Age	Path
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4656d 12h	/sdr_ctrl/trunk/rtl
38	Port Name clean up	dinesha	4657d 17h	/sdr_ctrl/trunk/rtl
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4657d 19h	/sdr_ctrl/trunk/rtl
36	Clean up	dinesha	4658d 10h	/sdr_ctrl/trunk/rtl
33	clean up	dinesha	4658d 12h	/sdr_ctrl/trunk/rtl
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4660d 11h	/sdr_ctrl/trunk/rtl
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4662d 15h	/sdr_ctrl/trunk/rtl
16	8 Bit SDRAM Support is added	dinesha	4664d 10h	/sdr_ctrl/trunk/rtl
15	Port cleanup	dinesha	4667d 10h	/sdr_ctrl/trunk/rtl
13	column bit are made progrmmable	dinesha	4667d 11h	/sdr_ctrl/trunk/rtl
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4671d 11h	/sdr_ctrl/trunk/rtl
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4672d 09h	/sdr_ctrl/trunk/rtl
3	SDRAM controller core files are checked in	dinesha	4678d 19h	/sdr_ctrl/trunk/rtl
2		dinesha	4681d 11h	/sdr_ctrl/trunk/rtl