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[/] [sdr_ctrl/] [trunk/] [rtl] - Rev 42

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Rev Log message Author Age Path
42 Bug fix in read access is fixed dinesha 4517d 12h /sdr_ctrl/trunk/rtl
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4518d 06h /sdr_ctrl/trunk/rtl
38 Port Name clean up dinesha 4519d 11h /sdr_ctrl/trunk/rtl
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4519d 13h /sdr_ctrl/trunk/rtl
36 Clean up dinesha 4520d 04h /sdr_ctrl/trunk/rtl
33 clean up dinesha 4520d 06h /sdr_ctrl/trunk/rtl
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4522d 05h /sdr_ctrl/trunk/rtl
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4524d 09h /sdr_ctrl/trunk/rtl
16 8 Bit SDRAM Support is added dinesha 4526d 04h /sdr_ctrl/trunk/rtl
15 Port cleanup dinesha 4529d 05h /sdr_ctrl/trunk/rtl
13 column bit are made progrmmable dinesha 4529d 05h /sdr_ctrl/trunk/rtl
9 SDR Bus width parameter passing issue across the models are fixed dinesha 4533d 06h /sdr_ctrl/trunk/rtl
4 Sdram controller RTL bug fixes done for 16bit SDR Mode dinesha 4534d 03h /sdr_ctrl/trunk/rtl
3 SDRAM controller core files are checked in dinesha 4540d 13h /sdr_ctrl/trunk/rtl
2 dinesha 4543d 06h /sdr_ctrl/trunk/rtl

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