URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl] - Rev 44

Rev	Log message	Author	Age	Path
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4506d 15h	/sdr_ctrl/trunk/rtl
42	Bug fix in read access is fixed	dinesha	4506d 17h	/sdr_ctrl/trunk/rtl
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4507d 12h	/sdr_ctrl/trunk/rtl
38	Port Name clean up	dinesha	4508d 17h	/sdr_ctrl/trunk/rtl
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4508d 19h	/sdr_ctrl/trunk/rtl
36	Clean up	dinesha	4509d 10h	/sdr_ctrl/trunk/rtl
33	clean up	dinesha	4509d 12h	/sdr_ctrl/trunk/rtl
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4511d 11h	/sdr_ctrl/trunk/rtl
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4513d 15h	/sdr_ctrl/trunk/rtl
16	8 Bit SDRAM Support is added	dinesha	4515d 10h	/sdr_ctrl/trunk/rtl
15	Port cleanup	dinesha	4518d 10h	/sdr_ctrl/trunk/rtl
13	column bit are made progrmmable	dinesha	4518d 11h	/sdr_ctrl/trunk/rtl
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4522d 11h	/sdr_ctrl/trunk/rtl
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4523d 09h	/sdr_ctrl/trunk/rtl
3	SDRAM controller core files are checked in	dinesha	4529d 19h	/sdr_ctrl/trunk/rtl
2		dinesha	4532d 11h	/sdr_ctrl/trunk/rtl