OpenCores
URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [rtl] - Rev 66

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4386d 07h /sdr_ctrl/trunk/rtl
64 CAS Latency support added for 4,5 dinesha 4386d 15h /sdr_ctrl/trunk/rtl
61 RTL file list are added into SVN dinesha 4505d 15h /sdr_ctrl/trunk/rtl
60 warning cleanup dinesha 4505d 15h /sdr_ctrl/trunk/rtl
59 Control path request and data are register now for better FPGA timing dinesha 4505d 15h /sdr_ctrl/trunk/rtl
58 Read Data is register on RD_FAST=0 case dinesha 4505d 15h /sdr_ctrl/trunk/rtl
55 FPGA Synthesis timing optimisation dinesha 4506d 06h /sdr_ctrl/trunk/rtl
54 FPGA Timing Optimisation dinesha 4509d 04h /sdr_ctrl/trunk/rtl
51 FPGA relating timing optimisation done dinesha 4510d 05h /sdr_ctrl/trunk/rtl
50 Bug fix the request length is fixe dinesha 4512d 09h /sdr_ctrl/trunk/rtl
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4513d 08h /sdr_ctrl/trunk/rtl
46 test bench upgrade + rtl cleanup dinesha 4515d 09h /sdr_ctrl/trunk/rtl
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4515d 13h /sdr_ctrl/trunk/rtl
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4517d 11h /sdr_ctrl/trunk/rtl
42 Bug fix in read access is fixed dinesha 4517d 13h /sdr_ctrl/trunk/rtl
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4518d 07h /sdr_ctrl/trunk/rtl
38 Port Name clean up dinesha 4519d 13h /sdr_ctrl/trunk/rtl
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4519d 14h /sdr_ctrl/trunk/rtl
36 Clean up dinesha 4520d 05h /sdr_ctrl/trunk/rtl
33 clean up dinesha 4520d 07h /sdr_ctrl/trunk/rtl

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.