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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

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[/] [sdr_ctrl/] [trunk/] [verif/] - Rev 36

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Rev Log message Author Age Path
33 clean up dinesha 4516d 13h /sdr_ctrl/trunk/verif
32 Debug is enable through +define dinesha 4518d 12h /sdr_ctrl/trunk/verif
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4518d 12h /sdr_ctrl/trunk/verif
29 SDRAM top and core related run file list are added into svn dinesha 4518d 12h /sdr_ctrl/trunk/verif
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4518d 12h /sdr_ctrl/trunk/verif
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4519d 10h /sdr_ctrl/trunk/verif
26 invalid log files are removed dinesha 4519d 10h /sdr_ctrl/trunk/verif
25 tb.sv is renamed as tb_top dinesha 4519d 11h /sdr_ctrl/trunk/verif
24 Clean Up dinesha 4519d 11h /sdr_ctrl/trunk/verif
22 Pad sdram clock added dinesha 4520d 16h /sdr_ctrl/trunk/verif
21 Clean up dinesha 4520d 16h /sdr_ctrl/trunk/verif
20 8 Bit SDARM support is added dinesha 4522d 11h /sdr_ctrl/trunk/verif
19 8 Bit SDRAM Support added dinesha 4522d 11h /sdr_ctrl/trunk/verif
18 8 Bit SDRAM Support is added dinesha 4522d 11h /sdr_ctrl/trunk/verif
17 micron 8 bit memory models are added into svn dinesha 4522d 11h /sdr_ctrl/trunk/verif
14 Unnecessary device config are removed dinesha 4525d 12h /sdr_ctrl/trunk/verif
12 Column Bits are made programmable dinesha 4525d 12h /sdr_ctrl/trunk/verif
10 Waveform files are added into SVN dinesha 4528d 13h /sdr_ctrl/trunk/verif
8 test bench files are added into SVN dinesha 4529d 13h /sdr_ctrl/trunk/verif
7 SDRAM Memory Models are added into SVN dinesha 4529d 13h /sdr_ctrl/trunk/verif

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