URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_SDR_32BIT_basic_test1.log] - Rev 65

Rev	Log message	Author	Age	Path
65	Updated Log file with CAS latency support 4,5	dinesha	4528d 04h	/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
56	FPGA Synth optimisation	dinesha	4647d 19h	/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
53	Test bench upgradation	dinesha	4651d 18h	/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
48	top-level cleanup	dinesha	4654d 21h	/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
46	test bench upgrade + rtl cleanup	dinesha	4656d 22h	/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4657d 02h	/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4659d 02h	/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
39	Test Bench upgradation with bigger data burst size	dinesha	4659d 21h	/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4661d 03h	/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4663d 20h	/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log