URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log/] [top_sdr32_sim.log] - Rev 45

Rev	Log message	Author	Age	Path
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4657d 05h	/sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4659d 05h	/sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
39	Test Bench upgradation with bigger data burst size	dinesha	4660d 00h	/sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4661d 07h	/sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4663d 23h	/sdr_ctrl/trunk/verif/log/top_sdr32_sim.log