URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log] - Rev 37

Rev	Log message	Author	Age	Path
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4515d 16h	/sdr_ctrl/trunk/verif/log
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4518d 08h	/sdr_ctrl/trunk/verif/log
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4519d 06h	/sdr_ctrl/trunk/verif/log
26	invalid log files are removed	dinesha	4519d 06h	/sdr_ctrl/trunk/verif/log
21	Clean up	dinesha	4520d 12h	/sdr_ctrl/trunk/verif/log
20	8 Bit SDARM support is added	dinesha	4522d 06h	/sdr_ctrl/trunk/verif/log
6	Golden Log files are added into SVN	dinesha	4529d 08h	/sdr_ctrl/trunk/verif/log
2		dinesha	4539d 08h	/sdr_ctrl/trunk/verif/log