URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [log] - Rev 49

Rev	Log message	Author	Age	Path
49	clean up	dinesha	4499d 03h	/sdr_ctrl/trunk/verif/log
48	top-level cleanup	dinesha	4499d 03h	/sdr_ctrl/trunk/verif/log
46	test bench upgrade + rtl cleanup	dinesha	4501d 04h	/sdr_ctrl/trunk/verif/log
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4501d 08h	/sdr_ctrl/trunk/verif/log
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4503d 06h	/sdr_ctrl/trunk/verif/log
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4503d 08h	/sdr_ctrl/trunk/verif/log
39	Test Bench upgradation with bigger data burst size	dinesha	4504d 02h	/sdr_ctrl/trunk/verif/log
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4505d 09h	/sdr_ctrl/trunk/verif/log
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4508d 01h	/sdr_ctrl/trunk/verif/log
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4509d 00h	/sdr_ctrl/trunk/verif/log
26	invalid log files are removed	dinesha	4509d 00h	/sdr_ctrl/trunk/verif/log
21	Clean up	dinesha	4510d 05h	/sdr_ctrl/trunk/verif/log
20	8 Bit SDARM support is added	dinesha	4512d 00h	/sdr_ctrl/trunk/verif/log
6	Golden Log files are added into SVN	dinesha	4519d 02h	/sdr_ctrl/trunk/verif/log
2		dinesha	4529d 02h	/sdr_ctrl/trunk/verif/log