URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 73

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Rev	Log message	Author	Age	Path
73	sdram bug in FPGA mode + 8/16 bit address map fix	dinesha	1185d 01h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
70	Warning Cleanup	dinesha	4230d 01h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
68	SDRAM Address bit increased from 12 bit to 13 bit	dinesha	4230d 02h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
56	FPGA Synth optimisation	dinesha	4668d 01h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
53	Test bench upgradation	dinesha	4671d 23h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
48	top-level cleanup	dinesha	4675d 03h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
46	test bench upgrade + rtl cleanup	dinesha	4677d 03h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4677d 08h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4679d 06h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4679d 08h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
39	Test Bench upgradation with bigger data burst size	dinesha	4680d 02h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
38	Port Name clean up	dinesha	4681d 07h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4681d 09h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4684d 01h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
25	tb.sv is renamed as tb_top	dinesha	4685d 00h	/sdr_ctrl/trunk/verif/tb/tb_top.sv
24	Clean Up	dinesha	4685d 00h	/sdr_ctrl/trunk/verif/tb/tb.sv
22	Pad sdram clock added	dinesha	4686d 05h	/sdr_ctrl/trunk/verif/tb/tb.sv
18	8 Bit SDRAM Support is added	dinesha	4688d 00h	/sdr_ctrl/trunk/verif/tb/tb.sv
14	Unnecessary device config are removed	dinesha	4691d 01h	/sdr_ctrl/trunk/verif/tb/tb.sv
12	Column Bits are made programmable	dinesha	4691d 01h	/sdr_ctrl/trunk/verif/tb/tb.sv

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Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] [tb_top.sv] - Rev 73

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