URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk] - Rev 19

Rev	Log message	Author	Age	Path
19	8 Bit SDRAM Support added	dinesha	4503d 20h	/sdr_ctrl/trunk
18	8 Bit SDRAM Support is added	dinesha	4503d 20h	/sdr_ctrl/trunk
17	micron 8 bit memory models are added into svn	dinesha	4503d 20h	/sdr_ctrl/trunk
16	8 Bit SDRAM Support is added	dinesha	4503d 20h	/sdr_ctrl/trunk
15	Port cleanup	dinesha	4506d 21h	/sdr_ctrl/trunk
14	Unnecessary device config are removed	dinesha	4506d 21h	/sdr_ctrl/trunk
13	column bit are made progrmmable	dinesha	4506d 21h	/sdr_ctrl/trunk
12	Column Bits are made programmable	dinesha	4506d 21h	/sdr_ctrl/trunk
11	SDRAM Specification document added into SVN	dinesha	4509d 22h	/sdr_ctrl/trunk
10	Waveform files are added into SVN	dinesha	4509d 22h	/sdr_ctrl/trunk
9	SDR Bus width parameter passing issue across the models are fixed	dinesha	4510d 22h	/sdr_ctrl/trunk
8	test bench files are added into SVN	dinesha	4510d 22h	/sdr_ctrl/trunk
7	SDRAM Memory Models are added into SVN	dinesha	4510d 22h	/sdr_ctrl/trunk
6	Golden Log files are added into SVN	dinesha	4510d 22h	/sdr_ctrl/trunk
5	Run files are updated into SVN	dinesha	4510d 22h	/sdr_ctrl/trunk
4	Sdram controller RTL bug fixes done for 16bit SDR Mode	dinesha	4511d 19h	/sdr_ctrl/trunk
3	SDRAM controller core files are checked in	dinesha	4518d 05h	/sdr_ctrl/trunk
2		dinesha	4520d 21h	/sdr_ctrl/trunk
1	The project and the structure was created	root	4524d 21h	/sdr_ctrl/trunk