URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk] - Rev 30

Rev	Log message	Author	Age	Path
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4519d 01h	/sdr_ctrl/trunk
29	SDRAM top and core related run file list are added into svn	dinesha	4519d 01h	/sdr_ctrl/trunk
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4519d 01h	/sdr_ctrl/trunk
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4520d 00h	/sdr_ctrl/trunk
26	invalid log files are removed	dinesha	4520d 00h	/sdr_ctrl/trunk
25	tb.sv is renamed as tb_top	dinesha	4520d 00h	/sdr_ctrl/trunk
24	Clean Up	dinesha	4520d 00h	/sdr_ctrl/trunk
23	Pad sdram clock added and read path register w.r.t pad sdram clock	dinesha	4521d 05h	/sdr_ctrl/trunk
22	Pad sdram clock added	dinesha	4521d 05h	/sdr_ctrl/trunk
21	Clean up	dinesha	4521d 05h	/sdr_ctrl/trunk
20	8 Bit SDARM support is added	dinesha	4523d 00h	/sdr_ctrl/trunk
19	8 Bit SDRAM Support added	dinesha	4523d 00h	/sdr_ctrl/trunk
18	8 Bit SDRAM Support is added	dinesha	4523d 00h	/sdr_ctrl/trunk
17	micron 8 bit memory models are added into svn	dinesha	4523d 00h	/sdr_ctrl/trunk
16	8 Bit SDRAM Support is added	dinesha	4523d 00h	/sdr_ctrl/trunk
15	Port cleanup	dinesha	4526d 01h	/sdr_ctrl/trunk
14	Unnecessary device config are removed	dinesha	4526d 01h	/sdr_ctrl/trunk
13	column bit are made progrmmable	dinesha	4526d 01h	/sdr_ctrl/trunk
12	Column Bits are made programmable	dinesha	4526d 01h	/sdr_ctrl/trunk
11	SDRAM Specification document added into SVN	dinesha	4529d 02h	/sdr_ctrl/trunk