URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk] - Rev 65

Rev	Log message	Author	Age	Path
65	Updated Log file with CAS latency support 4,5	dinesha	4378d 13h	/sdr_ctrl/trunk
64	CAS Latency support added for 4,5	dinesha	4378d 13h	/sdr_ctrl/trunk
63	FPGA Bench mark results are added	dinesha	4497d 12h	/sdr_ctrl/trunk
62	Synthesis constraint for simplify	dinesha	4497d 13h	/sdr_ctrl/trunk
61	RTL file list are added into SVN	dinesha	4497d 13h	/sdr_ctrl/trunk
60	warning cleanup	dinesha	4497d 13h	/sdr_ctrl/trunk
59	Control path request and data are register now for better FPGA timing	dinesha	4497d 13h	/sdr_ctrl/trunk
58	Read Data is register on RD_FAST=0 case	dinesha	4497d 13h	/sdr_ctrl/trunk
57	Synthesis constraints are added	dinesha	4498d 04h	/sdr_ctrl/trunk
56	FPGA Synth optimisation	dinesha	4498d 05h	/sdr_ctrl/trunk
55	FPGA Synthesis timing optimisation	dinesha	4498d 05h	/sdr_ctrl/trunk
54	FPGA Timing Optimisation	dinesha	4501d 03h	/sdr_ctrl/trunk
53	Test bench upgradation	dinesha	4502d 03h	/sdr_ctrl/trunk
52	Documentation update for request control and transfer control block	dinesha	4502d 03h	/sdr_ctrl/trunk
51	FPGA relating timing optimisation done	dinesha	4502d 04h	/sdr_ctrl/trunk
50	Bug fix the request length is fixe	dinesha	4504d 07h	/sdr_ctrl/trunk
49	clean up	dinesha	4505d 06h	/sdr_ctrl/trunk
48	top-level cleanup	dinesha	4505d 06h	/sdr_ctrl/trunk
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4505d 07h	/sdr_ctrl/trunk
46	test bench upgrade + rtl cleanup	dinesha	4507d 07h	/sdr_ctrl/trunk