URL https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk

Subversion Repositories sdram_controller

[/] [sdram_controller] - Rev 9

Rev	Log message	Author	Age	Path
9	Got rid of some redundant busy_n <= '0' statements	lynn0p	5389d 15h	/sdram_controller
8	Changes made to integrate and test with my homebrew SoC design. 1. One DCM has been removed. Now requires a 100mhz clock fed in. Only consumes one DCM, if you can find a 100mhz clock somewhere. 2. Small timing modifications to fix memory glitches between controller and the t80 soft cpu I'm using.	lynn0p	5389d 15h	/sdram_controller
7	Reformatted the comments so they fit in 80 columns	lynn0p	5397d 20h	/sdram_controller
6	changes to reduce synthesizer warnings, removed unused signals, etc.	lynn0p	5398d 00h	/sdram_controller
5	added header file for ddr.v	lynn0p	5398d 20h	/sdram_controller
4	added testbench files to trunk	lynn0p	5398d 20h	/sdram_controller
3	adding LGPLv3 license file	lynn0p	5398d 20h	/sdram_controller
2	initial checkin	lynn0p	5398d 20h	/sdram_controller
1	The project was created and the structure was created	root	5399d 00h	/sdram_controller